1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating such semiconductor device. The invention is particularly well adapted for semiconductor devices having various interconnection wiring layers, such as logic LSIs and DRAMs.
2. Description of the Related Art
In association with recent trend towards the miniaturization and higher integration of semiconductor elements, the distance between a plurality of adjacent interconnection runners is reduced, and this has imposed the problem of increased RC (resistance and capacitance) delay in interconnections caused by increased parasitic capacitance between interconnection runners. To reduce the parasitic capacitances between interconnections most effectively, attempts have been made to provide an air gap between a plurality of interconnection runners arranged on a single layer.
For example, JP-A-7-45701 discloses a method of fabricating a semiconductor device involving the steps of forming a plurality of interconnections on a single layer, forming a solid film (ice) by cooling with a liquid; removing the solid film until the interconnection portions are exposed, forming a coarse insulating film having a large shrinking rate, evaporating the solid film through the coarse insulating film by vaporizing the solid film by heat or the like, and forming a dense insulating film having a shrinking rate which is smaller than that of the coarse insulating film. This method provides the air gap between interconnections, but brings about, at the same time, a fear that the residual moisture will corrode the interconnections.
Similarly, JP-A-9-172068 discloses a fabrication method using an organic resin film as the solid film in place of ice and using an organic SOG (spin on glass) as the coarse insulating film and involving the step of removing the organic resin film through the organic SOG film by means of an O.sub.2 plasma process or the like. However, it is extremely difficult to remove the organic resin film completely.
Further, JP-A-9-129726 discloses a semiconductor device of a multilevel metallization (wiring) structure in which first and second interconnection wiring layers formed over the first interconnection wiring layers are arranged on a semiconductor substrate. The structural feature of this semiconductor device is such that a vacuum or a gas such as air is present between a plurality of the first interconnection wiring layers arranged on a single layer. To fabricate this semiconductor device, an interlayer insulating film composed of a polyimide film is adhered onto the first interconnection wiring layers, and then etched using a photoresist as a mask to form throughholes. Then, a tungsten plug is formed within each throughhole. Thereafter, an aluminum alloy film is deposited on the resultant, and then etched using a photoresist as a mask to form the second interconnection wiring layers. This fabrication method also provides an air gap between interconnection wiring layers, but still imposes problems since the polyimide film is less heat-resistant and degasses in large amounts. In addition, the polyimide film must have a certain thickness to be adhered onto the first interconnection wiring layers.
Furthermore, JP-A-9-186232 discloses a method of fabricating a semiconductor device involving the steps of forming a first interlayer insulating film on the surfaces of first interconnection wiring layers formed on a semiconductor substrate, forming a second interlayer insulating film so as to bury recesses formed in the first interlayer insulating film, forming a third interlayer insulating film that is deposited on both the first and second interlayer insulating films, and forming cavities in the recesses first by etching the third interlayer insulating film using a throughhole-patterned masking resist and then by etching the second interlayer insulating film exposed by the preceding etching process to thereby remove the second interlayer insulating film buried in the recesses. However, an air gap cannot be provided in all the spaces between the first interconnection wiring layers since the first interlayer insulating film remains on the first interconnection wiring layers.